אינדקס
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The ARM® Cortex®-A57 processor is ARM’s highest performing processor, designed to further extend the capabilities of future mobile and enterprise computing applications including compute intensive 64-bit applications such as high end computer, tablet and server products.
The processor can be implemented individually or paired with the Cortex-A53 processor into an ARM big.LITTLE configuration that enables scalable performance and optimal energy-efficiency.
Cortex-A57 MPCore
Architecture ARMv8-A
Multicore
1-4X SMP within a single processor cluster
Multiple coherent SMP processor clusters through AMBA® 5 CHI or AMBA® 4 ACE technology
ISA Support
AArch32 for full backward compatibility with ARMv7
AArch64 for 64-bit support and new architectural features
TrustZone® security technology
NEON™ Advanced SIMD
DSP & SIMD extensions
VFPv4 Floating point
Hardware virtualization support
Debug & Trace CoreSight™ DK-A57
The Cortex-A57 MPCore processor incorporates a broad range of ARM technology including System IP, Physical IP, and development tools that also provide support. A broad range of SoC and software design solutions, tools and services from the ARM Connected Community™ compliment this technology. That provides ARM Partners with a smooth path through the development, verification and production of full function, compelling devices while significantly reducing time-to-market.
System IP
The ARM CoreLink™ interconnect and memory controller system IP addresses the critical challenge of efficiently moving and storing data between up to 16 Cortex-A series processors, high-performance media processors and dynamic memories to optimize the system performance and power consumption of the SoC. The CoreLink system IP enables SoC designers to maximize the utilization of system memory bandwidth and reduce static and dynamic latencies. While the ARM CoreSight technology provides complete on-chip debug and correlated, real-time trace visibility for all cores of the Cortex-A57 MPCore processor, reducing risk and speeding development of high-quality multiprocessing software. The new ARM CoreLink CCN-504 Cache Coherent Network provides optimum system bandwidth and latency. The CCN-504 provides AMBA 4 AXI™ Coherency Extensions (ACE) compliant ports for full coherency between multiple Cortex-A series processors, better utilizing caches and simplifying software development. This feature is essential for high-bandwidth applications including gaming, servers and networking that require clusters of coherent single and multicore processors. Combined with the ARM CoreLink network interconnect and memory controller IP, the CCN increases system performance and power efficiency.
The CoreLink CCI-400 Cache Coherent Interconnect provides the big.LITTLE interconnect for use with Cortex-A53 for client applications including smartphone and tablet application processors.
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הקהילה מציעה ממירים חדשים מבוססי CORTEX ARM עבור השוק הסיני
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Cortex-A9 Processor
Cortex-A9 Processor Image
(View Larger Cortex-A9 Processor Image)
The ARM® Cortex®-A9 processor is the power-efficient and popular high performance choice in low power or thermally constrained cost-sensitive devices.
It is currently shipping in increasing volumes in smartphones, digital TV, consumer and enterprise applications enabling your connected life. Cortex-A9 is available as a single processor solution offering an overall performance enhancement of well above 50% compared to ARM Cortex-A8 solutions. Cortex-A9 MPCore offers up to four processors delivering when needed, on lightweight workload as well as peak performance. Its configurability and flexibility allows Cortex-A9 to scale across a wide variety of markets and applications.
Cortex-A9 is available with either synthesizable or hard-macro implementations. ARM Physical IP is available to support a synthesizable flow optimized for lowest power or highest performance, as well as a choice of hard-macros reducing risk and shortening time-to-market to a minimum. Enhanced ARM Graphics IP like Mali-T624 as well as ARM System IP such as CoreLink NIC-400/301 network interconnect and CoreLink DMC-342 dynamic memory controller allow a rapid system design. ARM Development Suite 5 (DS-5™) tools and enhanced CoreSight Debug & Trace IP like CoreSight SoC-400 and CoreSight Design Kit for Cortex-A9 (DK-A9) allow instant software development that is backed by a broad software ecosystem.
Industry Standard
Cortex-A series processors are used in a wide variety of performance applications. As a result, they offer significantly different power and performance characteristics to ensure the right-fit for advanced embedded solutions demanding a feature-rich operating system and a wide variety of mobile and consumer applications.
Cortex-A Comparisons
All Cortex-A based processors share a commonly supported architecture and feature set. This makes them the best solution for open platform design where compatibility and portability of software between designs is of upmost importance:
All Cortex-A processors suupport ARMv8-A or ARMv7-A architecture and feature set. The ARMv8-A architecture has a 64-bit execution state and can also support existing 32-bit applications. This backwards compatibility strengthens the 64-bit ecosystem
Support for full Operating Systems
Linux full distributions- Android, Chrome, Ubuntu and Debian
Linux 3rd party - MontaVista, QNX, Wind River
Symbian
Windows CE
Other OS support requiring Memory Management Unit
Instruction Set Support - ARM, Thumb-2, Thumb, Jazelle®, DSP
TrustZone® Security Extensions
Advanced single-precision and double-precision Floating Point support
NEON™ media processing engine
Virtualization
1TB addressing (LPAE)
Together, the range of Cortex-A processors provide design flexibility by providing the required peak performance points and scalability, and delivering the desired power efficiency and silicon cost while maintaining full software compatibility.
Cortex-A Technologies
The Cortex-A processors share a number of key technologies that make them ideal for portable media-rich devices.
RISC Processor Core Instruction Set Architecture
High performance 32-bit & 64-bit cores
15-stage+ pipeline technology
1.5-3.5+ DMIPS/MHz per core
Advanced branch prediction
ARM and Thumb ISA for ensuring binary compatibility
Thumb-2 for optimal blend of code density and performance
NEON™ / DSP extensions for advanced DSP and media performance
VFP for high-performance single and double-precision floating point
Jazelle®-DBX and RCT support
Media Acceleration Multicore Technologies
NEON integer and floating point SIMD Engine for enhanced media performance
Jazelle technology for accelerated execution environments
1-4 cores
Full L1 cache coherency
Advanced Coherency Port
Snoop Control Unit
Advanced Memory System System Extensions
1-2 cycle cache access
Pipe-lined loads and stores
Tuned for memory streaming
Integrated or closely-coupled optional level-2 caches
TrustZone® security extensions
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In addition to the single and multicore soft processors, the Cortex-A9 product portfolio also includes two popular dual-core hard-macro implementations for the TSMC 40G and 40LP processes.
These hard macro implementations provide the fastest time to market for SoC designers, through a ready to use, best in class solution. They also significantly reduce the implementation costs. These macros utilize the ARM Physical IP POP and advanced, aggressive low-power implementation techniques to deliver a highly optimized and assured PPA within the power envelope of compact, high-density and thermally constrained environments. The integrated design allows SoC designers time to focus on their key capabilities.
Dual Cortex-A9 TSMC 40G Hard Macro (Power Optimized): In many thermally constrained applications such as set-top boxes, DTVs, printers and other feature-rich consumer and high-density enterprise applications, energy efficiency is of paramount importance. The Cortex-A9 power-optimized hard macro implementation delivers its peak performance of 4000 DMIPS while consuming less than 250mW per CPU when selected from typical silicon.
Dual Cortex-A9 TSMC 40LP Hard Macro (Performance Optimized): This implementation is optimized to obtain the best performance on the low power TSMC 40LP process. Ideally suited to SoCs operating within a tight power budget, yet wishing to provide a high level of performance and functionality, this hard macro is capable of delivering 1GHz+ performance. The implementation builds upon the inherent low power capabilities of TSMC40LP process through a strong design focus on reducing leakage and dynamic power while maintaining high performance levels.
The hard macro implementations include ARM AMBA-compliant high performance system components to maximize data traffic speed and minimize power consumption and silicon area. Each Cortex-A9 hard macro implementation also includes the CoreSight™ Program Trace Macrocell (PTM) that provides full visibility into the processor’s instruction flow enabling the software community to develop code for optimal performance. Also included within the macro is the ARM high performance L2 cache controller supporting configurations between 128K and 8M of L2 cache memory.
The ARM® Cortex®-A57 processor is ARM’s highest performing processor, designed to further extend the capabilities of future mobile and enterprise computing applications including compute intensive 64-bit applications such as high end computer, tablet and server products.
The processor can be implemented individually or paired with the Cortex-A53 processor into an ARM big.LITTLE configuration that enables scalable performance and optimal energy-efficiency.
Cortex-A57 MPCore
Architecture ARMv8-A
Multicore
1-4X SMP within a single processor cluster
Multiple coherent SMP processor clusters through AMBA® 5 CHI or AMBA® 4 ACE technology
ISA Support
AArch32 for full backward compatibility with ARMv7
AArch64 for 64-bit support and new architectural features
TrustZone® security technology
NEON™ Advanced SIMD
DSP & SIMD extensions
VFPv4 Floating point
Hardware virtualization support
Debug & Trace CoreSight™ DK-A57
The Cortex-A57 MPCore processor incorporates a broad range of ARM technology including System IP, Physical IP, and development tools that also provide support. A broad range of SoC and software design solutions, tools and services from the ARM Connected Community™ compliment this technology. That provides ARM Partners with a smooth path through the development, verification and production of full function, compelling devices while significantly reducing time-to-market.
System IP
The ARM CoreLink™ interconnect and memory controller system IP addresses the critical challenge of efficiently moving and storing data between up to 16 Cortex-A series processors, high-performance media processors and dynamic memories to optimize the system performance and power consumption of the SoC. The CoreLink system IP enables SoC designers to maximize the utilization of system memory bandwidth and reduce static and dynamic latencies. While the ARM CoreSight technology provides complete on-chip debug and correlated, real-time trace visibility for all cores of the Cortex-A57 MPCore processor, reducing risk and speeding development of high-quality multiprocessing software. The new ARM CoreLink CCN-504 Cache Coherent Network provides optimum system bandwidth and latency. The CCN-504 provides AMBA 4 AXI™ Coherency Extensions (ACE) compliant ports for full coherency between multiple Cortex-A series processors, better utilizing caches and simplifying software development. This feature is essential for high-bandwidth applications including gaming, servers and networking that require clusters of coherent single and multicore processors. Combined with the ARM CoreLink network interconnect and memory controller IP, the CCN increases system performance and power efficiency.
The CoreLink CCI-400 Cache Coherent Interconnect provides the big.LITTLE interconnect for use with Cortex-A53 for client applications including smartphone and tablet application processors.
=================================================
הקהילה מציעה ממירים חדשים מבוססי CORTEX ARM עבור השוק הסיני
[You must be registered and logged in to see this image.]
Cortex-A9 Processor
Cortex-A9 Processor Image
(View Larger Cortex-A9 Processor Image)
The ARM® Cortex®-A9 processor is the power-efficient and popular high performance choice in low power or thermally constrained cost-sensitive devices.
It is currently shipping in increasing volumes in smartphones, digital TV, consumer and enterprise applications enabling your connected life. Cortex-A9 is available as a single processor solution offering an overall performance enhancement of well above 50% compared to ARM Cortex-A8 solutions. Cortex-A9 MPCore offers up to four processors delivering when needed, on lightweight workload as well as peak performance. Its configurability and flexibility allows Cortex-A9 to scale across a wide variety of markets and applications.
Cortex-A9 is available with either synthesizable or hard-macro implementations. ARM Physical IP is available to support a synthesizable flow optimized for lowest power or highest performance, as well as a choice of hard-macros reducing risk and shortening time-to-market to a minimum. Enhanced ARM Graphics IP like Mali-T624 as well as ARM System IP such as CoreLink NIC-400/301 network interconnect and CoreLink DMC-342 dynamic memory controller allow a rapid system design. ARM Development Suite 5 (DS-5™) tools and enhanced CoreSight Debug & Trace IP like CoreSight SoC-400 and CoreSight Design Kit for Cortex-A9 (DK-A9) allow instant software development that is backed by a broad software ecosystem.
Industry Standard
Cortex-A series processors are used in a wide variety of performance applications. As a result, they offer significantly different power and performance characteristics to ensure the right-fit for advanced embedded solutions demanding a feature-rich operating system and a wide variety of mobile and consumer applications.
Cortex-A Comparisons
All Cortex-A based processors share a commonly supported architecture and feature set. This makes them the best solution for open platform design where compatibility and portability of software between designs is of upmost importance:
All Cortex-A processors suupport ARMv8-A or ARMv7-A architecture and feature set. The ARMv8-A architecture has a 64-bit execution state and can also support existing 32-bit applications. This backwards compatibility strengthens the 64-bit ecosystem
Support for full Operating Systems
Linux full distributions- Android, Chrome, Ubuntu and Debian
Linux 3rd party - MontaVista, QNX, Wind River
Symbian
Windows CE
Other OS support requiring Memory Management Unit
Instruction Set Support - ARM, Thumb-2, Thumb, Jazelle®, DSP
TrustZone® Security Extensions
Advanced single-precision and double-precision Floating Point support
NEON™ media processing engine
Virtualization
1TB addressing (LPAE)
Together, the range of Cortex-A processors provide design flexibility by providing the required peak performance points and scalability, and delivering the desired power efficiency and silicon cost while maintaining full software compatibility.
Cortex-A Technologies
The Cortex-A processors share a number of key technologies that make them ideal for portable media-rich devices.
RISC Processor Core Instruction Set Architecture
High performance 32-bit & 64-bit cores
15-stage+ pipeline technology
1.5-3.5+ DMIPS/MHz per core
Advanced branch prediction
ARM and Thumb ISA for ensuring binary compatibility
Thumb-2 for optimal blend of code density and performance
NEON™ / DSP extensions for advanced DSP and media performance
VFP for high-performance single and double-precision floating point
Jazelle®-DBX and RCT support
Media Acceleration Multicore Technologies
NEON integer and floating point SIMD Engine for enhanced media performance
Jazelle technology for accelerated execution environments
1-4 cores
Full L1 cache coherency
Advanced Coherency Port
Snoop Control Unit
Advanced Memory System System Extensions
1-2 cycle cache access
Pipe-lined loads and stores
Tuned for memory streaming
Integrated or closely-coupled optional level-2 caches
TrustZone® security extensions
[You must be registered and logged in to see this image.]
In addition to the single and multicore soft processors, the Cortex-A9 product portfolio also includes two popular dual-core hard-macro implementations for the TSMC 40G and 40LP processes.
These hard macro implementations provide the fastest time to market for SoC designers, through a ready to use, best in class solution. They also significantly reduce the implementation costs. These macros utilize the ARM Physical IP POP and advanced, aggressive low-power implementation techniques to deliver a highly optimized and assured PPA within the power envelope of compact, high-density and thermally constrained environments. The integrated design allows SoC designers time to focus on their key capabilities.
Dual Cortex-A9 TSMC 40G Hard Macro (Power Optimized): In many thermally constrained applications such as set-top boxes, DTVs, printers and other feature-rich consumer and high-density enterprise applications, energy efficiency is of paramount importance. The Cortex-A9 power-optimized hard macro implementation delivers its peak performance of 4000 DMIPS while consuming less than 250mW per CPU when selected from typical silicon.
Dual Cortex-A9 TSMC 40LP Hard Macro (Performance Optimized): This implementation is optimized to obtain the best performance on the low power TSMC 40LP process. Ideally suited to SoCs operating within a tight power budget, yet wishing to provide a high level of performance and functionality, this hard macro is capable of delivering 1GHz+ performance. The implementation builds upon the inherent low power capabilities of TSMC40LP process through a strong design focus on reducing leakage and dynamic power while maintaining high performance levels.
The hard macro implementations include ARM AMBA-compliant high performance system components to maximize data traffic speed and minimize power consumption and silicon area. Each Cortex-A9 hard macro implementation also includes the CoreSight™ Program Trace Macrocell (PTM) that provides full visibility into the processor’s instruction flow enabling the software community to develop code for optimal performance. Also included within the macro is the ARM high performance L2 cache controller supporting configurations between 128K and 8M of L2 cache memory.
