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מה זה מרובה מעבדים OCTACORE DUAL CORE QUAD CORE

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1 מה זה מרובה מעבדים OCTACORE DUAL CORE QUAD CORE Fri Dec 02, 2016 10:47 am

libsker

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יש הרבה ממירים מבוסס אנדרואיד שיוצאים עם הרבה ליבות
תחת המושגים
DUAL CORE
QUAD CORE
OCTA CORE
PENTA CORE

אלה חלק מהדגמים שקיימים כיום.

Multi-Core Microprocessors

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A penta-core [You must be registered and logged in to see this link.] refers to an [You must be registered and logged in to see this link.]that implements five independent physical execution units (referred to as [You must be registered and logged in to see this link.]) on a single [You must be registered and logged in to see this link.].

[You must be registered and logged in to see this link.]

[You must be registered and logged in to see this image.]

Terminology[[You must be registered and logged in to see this link.]]

The terms multi-core and dual-core most commonly refer to some sort of [You must be registered and logged in to see this link.] (CPU), but are sometimes also applied to [You must be registered and logged in to see this link.] (DSP) and [You must be registered and logged in to see this link.] (SoC). The terms are generally used only to refer to multi-core microprocessors that are manufactured on the same integrated circuit [You must be registered and logged in to see this link.]; separate microprocessor dies in the same package are generally referred to by another name, such as [You must be registered and logged in to see this link.]. This article uses the terms "multi-core" and "dual-core" for CPUs manufactured on the same integrated circuit, unless otherwise noted.
In contrast to multi-core systems, the term multi-CPU refers to multiple physically separate processing-units (which often contain special circuitry to facilitate communication between each other).
The terms many-core and massively multi-core are sometimes used to describe multi-core architectures with an especially high number of cores (tens or hundreds).^{[You must be registered and logged in to see this link.]}
Some systems use many [You must be registered and logged in to see this link.] cores placed on a single [You must be registered and logged in to see this link.]. Each "core" can be considered a "[You must be registered and logged in to see this link.]" as well as a CPU core.^{[[You must be registered and logged in to see this link.]]}

Development[[You must be registered and logged in to see this link.]]

While manufacturing technology improves, reducing the size of individual gates, physical limits of [You must be registered and logged in to see this link.]-based[You must be registered and logged in to see this link.] have become a major design concern. These physical limitations can cause significant heat dissipation and data synchronization problems. Various other methods are used to improve CPU performance. Some [You must be registered and logged in to see this link.] (ILP) methods such as [You must be registered and logged in to see this link.] [You must be registered and logged in to see this link.] are suitable for many applications, but are inefficient for others that contain difficult-to-predict code. Many applications are better suited to [You must be registered and logged in to see this link.] (TLP) methods, and multiple independent CPUs are commonly used to increase a system's overall TLP. A combination of increased available space (due to refined manufacturing processes) and the demand for increased TLP led to the development of multi-core CPUs.

Commercial incentives[[You must be registered and logged in to see this link.]]

Several business motives drive the development of multi-core architectures. For decades, it was possible to improve performance of a CPU by shrinking the area of the integrated circuit (IC), which reduced the cost per device on the IC. Alternatively, for the same circuit area, more transistors could be used in the design, which increased functionality, especially for [You must be registered and logged in to see this link.] (CISC) architectures. [You must be registered and logged in to see this link.] also increased by orders of magnitude in the decades of the late 20th century, from several megahertz in the 1980s to several gigahertz in the early 2000s.
As the rate of clock speed improvements slowed, increased use of parallel computing in the form of multi-core processors has been pursued to improve overall processing performance. Multiple cores were used on the same CPU chip, which could then lead to better sales of CPU chips with two or more cores. For example, Intel has produced a 48-core processor for research in cloud computing; each core has an [You must be registered and logged in to see this link.] architecture.^{[You must be registered and logged in to see this link.]}^{[You must be registered and logged in to see this link.]}

Technical factors[[You must be registered and logged in to see this link.]]

Since computer manufacturers have long implemented [You must be registered and logged in to see this link.] (SMP) designs using discrete CPUs, the issues regarding implementing multi-core processor architecture and supporting it with software are well known.
Additionally:

Using a proven processing-core design without architectural changes reduces design risk significantly.
For general-purpose processors, much of the motivation for multi-core processors comes from greatly diminished gains in processor performance from increasing the [You must be registered and logged in to see this link.]. This is due to three primary factors:^{[You must be registered and logged in to see this link.]}
[list="margin-top: 0.3em; margin-right: 0px; margin-left: 3.2em; padding-right: 0px; padding-left: 0px; list-style-image: none;"]
The memory wall; the increasing gap between processor and memory speeds. This, in effect, pushes for cache sizes to be larger in order to mask the latency of memory. This helps only to the extent that memory bandwidth is not the bottleneck in performance.
The ILP wall; the increasing difficulty of finding enough [You must be registered and logged in to see this link.] to keep a high-performance single-core processor busy.
The power wall; the trend of consuming exponentially increasing power with each factorial increase of operating frequency. This increase can be mitigated by "[You must be registered and logged in to see this link.]" the processor by using smaller traces for the same logic. The power wall poses manufacturing, system design and deployment problems that have not been justified in the face of the diminished gains in performance due to the memory wall and ILP wall.

[/list]
In order to continue delivering regular performance improvements for general-purpose processors, manufacturers such as[You must be registered and logged in to see this link.] and [You must be registered and logged in to see this link.] have turned to multi-core designs, sacrificing lower manufacturing-costs for higher performance in some applications and systems. Multi-core architectures are being developed, but so are the alternatives. An especially strong contender for established markets is the further integration of peripheral functions into the chip.

Advantages[[You must be registered and logged in to see this link.]]

The proximity of multiple CPU cores on the same die allows the [You must be registered and logged in to see this link.] circuitry to operate at a much higher clock rate than what is possible if the signals have to travel off-chip. Combining equivalent CPUs on a single die significantly improves the performance of [You must be registered and logged in to see this link.] (alternative: [You must be registered and logged in to see this link.]) operations. Put simply, this means that [You must be registered and logged in to see this link.]between different CPUs travel shorter distances, and therefore those signals [You must be registered and logged in to see this link.] less. These higher-quality signals allow more data to be sent in a given time period, since individual signals can be shorter and do not need to be repeated as often.
Assuming that the die can physically fit into the package, multi-core CPU designs require much less [You must be registered and logged in to see this link.](PCB) space than do multi-chip SMP designs. Also, a dual-core processor uses slightly less power than two coupled single-core processors, principally because of the decreased power required to drive signals external to the chip. Furthermore, the cores share some circuitry, like the L2 cache and the interface to the [You must be registered and logged in to see this link.] (FSB). In terms of competing technologies for the available silicon die area, multi-core design can make use of proven CPU core library designs and produce a product with lower risk of design error than devising a new wider-core design. Also, adding more cache suffers from diminishing returns.
Multi-core chips also allow higher performance at lower energy. This can be a big factor in mobile devices that operate on batteries. Since each core in a multi-core CPU is generally more energy-efficient, the chip becomes more efficient than having a single large monolithic core. This allows higher performance with less energy. A challenge in this, however, is the additional overhead of writing parallel code.^{[You must be registered and logged in to see this link.]}

Disadvantages[[You must be registered and logged in to see this link.]]

Maximizing the usage of the computing resources provided by multi-core processors requires adjustments both to the[You must be registered and logged in to see this link.] (OS) support and to existing application software. Also, the ability of multi-core processors to increase application performance depends on the use of multiple threads within applications.
Integration of a multi-core chip can lower the chip production yields. They are also more difficult to manage thermally than lower-density single-core designs. Intel has partially countered this first problem by creating its quad-core designs by combining two dual-core ones on a single die with a unified cache, hence any two working dual-core dies can be used, as opposed to producing four cores on a single die and requiring all four to work to produce a quad-core CPU. From an architectural point of view, ultimately, single CPU designs may make better use of the silicon surface area than multiprocessing cores, so a development commitment to this architecture may carry the risk of obsolescence. Finally, raw processing power is not the only constraint on system performance. Two processing cores sharing the same system bus and memory bandwidth limits the real-world performance advantage. It has been claimed^{[[You must be registered and logged in to see this link.]]} that if a single core is close to being memory-bandwidth limited, then going to dual-core might give 30% to 70% improvement; if memory bandwidth is not a problem, then a 90% improvement can be expected; however, [You must be registered and logged in to see this link.] makes this claim dubious.^{[You must be registered and logged in to see this link.]} It would be possible for an application that used two CPUs to end up running faster on a single-core one if communication between the CPUs was the limiting factor, which would count as more than 100% improvement.

Hardware[[You must be registered and logged in to see this link.]]

Trends[[You must be registered and logged in to see this link.]]

The trend in processor development has been towards an ever increasing number of cores, as processors with hundreds or even thousands of cores become theoretically possible.^{[You must be registered and logged in to see this link.]} In addition, multi-core chips mixed with [You must be registered and logged in to see this link.], memory-on-chip, and special-purpose [You must be registered and logged in to see this link.] (or asymmetric) cores promise further performance and efficiency gains,^{[You must be registered and logged in to see this link.]} especially in processing multimedia, recognition and networking applications. For example, a[You must be registered and logged in to see this link.] core includes a high-performance core (called 'big') and a low-power core (called 'LITTLE'). There is also a trend towards improving energy-efficiency by focusing on performance-per-watt with advanced fine-grain or ultra fine-grain [You must be registered and logged in to see this link.] and dynamic [You must be registered and logged in to see this link.] and [You must be registered and logged in to see this link.] (i.e. [You must be registered and logged in to see this link.] computers and [You must be registered and logged in to see this link.]).
Chips designed from the outset for a large number of cores (rather than having evolved from single core designs) are sometimes referred to as [You must be registered and logged in to see this link.] designs, emphasising qualitative differences.

Architecture[[You must be registered and logged in to see this link.]]

The composition and balance of the cores in multi-core architecture show great variety. Some architectures use one core design repeated consistently ("homogeneous"), while others use a mixture of different cores, each optimized for a different, "[You must be registered and logged in to see this link.]" role.
The article "CPU designers debate multi-core future" by Rick Merritt, EE Times 2008,^{[You must be registered and logged in to see this link.]} includes these comments:

Chuck Moore [...] suggested computers should be like cellphones, using a variety of specialty cores to run modular software scheduled by a high-level applications programming interface.
[...] Atsushi Hasegawa, a senior chief engineer at [You must be registered and logged in to see this link.], generally agreed. He suggested the cellphone's use of many specialty cores working in concert is a good model for future multi-core designs.
[...] [You must be registered and logged in to see this link.], founder and chief executive of startup [You must be registered and logged in to see this link.], took the opposing view. He said multi-core chips need to be homogeneous collections of general-purpose cores to keep the software model simple.

Software effects[[You must be registered and logged in to see this link.]]

An outdated version of an anti-virus application may create a new thread for a scan process, while its [You must be registered and logged in to see this link.] thread waits for commands from the user (e.g. cancel the scan). In such cases, a multi-core architecture is of little benefit for the application itself due to the single thread doing all the heavy lifting and the inability to balance the work evenly across multiple cores. Programming truly multithreaded code often requires complex co-ordination of threads and can easily introduce subtle and difficult-to-find bugs due to the interweaving of processing on data shared between threads (see [You must be registered and logged in to see this link.]). Consequently, such code is much more difficult to debug than single-threaded code when it breaks. There has been a perceived lack of motivation for writing consumer-level threaded applications because of the relative rarity of consumer-level demand for maximum use of computer hardware. Although threaded applications incur little additional performance penalty on single-processor machines, the extra overhead of development has been difficult to justify due to the preponderance of single-processor machines. Also, serial tasks like decoding the [You must be registered and logged in to see this link.] algorithms used in [You must be registered and logged in to see this link.] are impossible to parallelize because each result generated is used to help create the next result of the entropy decoding algorithm.
Given the increasing emphasis on multi-core chip design, stemming from the grave thermal and power consumption problems posed by any further significant increase in processor clock speeds, the extent to which software can be multithreaded to take advantage of these new chips is likely to be the single greatest constraint on computer performance in the future. If developers are unable to design software to fully exploit the resources provided by multiple cores, then they will ultimately reach an insurmountable performance ceiling.
The telecommunications market had been one of the first that needed a new design of parallel datapath packet processing because there was a very quick adoption of these multiple-core processors for the datapath and the control plane. These MPUs are going to replace^{[You must be registered and logged in to see this link.]} the traditional Network Processors that were based on proprietary [You must be registered and logged in to see this link.] or [You must be registered and logged in to see this link.].
[You must be registered and logged in to see this link.] techniques can benefit from multiple cores directly. Some existing [You must be registered and logged in to see this link.] such as [You must be registered and logged in to see this link.], [You must be registered and logged in to see this link.], [You must be registered and logged in to see this link.], [You must be registered and logged in to see this link.], Skandium, [You must be registered and logged in to see this link.], and [You must be registered and logged in to see this link.] can be used on multi-core platforms. Intel introduced a new abstraction for C++ parallelism called [You must be registered and logged in to see this link.]. Other research efforts include the [You must be registered and logged in to see this link.], Cray's [You must be registered and logged in to see this link.], Sun's [You must be registered and logged in to see this link.], and IBM's [You must be registered and logged in to see this link.].
Multi-core processing has also affected the ability of modern computational software development. Developers programming in newer languages might find that their modern languages do not support multi-core functionality. This then requires the use of [You must be registered and logged in to see this link.] to access code written in languages like [You must be registered and logged in to see this link.] and [You must be registered and logged in to see this link.], which perform math computations faster than newer languages like [You must be registered and logged in to see this link.]. Intel's MKL and AMD's [You must be registered and logged in to see this link.] are written in these native languages and take advantage of multi-core processing. Balancing the application workload across processors can be problematic, especially if they have different performance characteristics. There are different conceptual models to deal with the problem, for example using a coordination language and program building blocks (programming libraries or higher-order functions). Each block can have a different native implementation for each processor type. Users simply program using these abstractions and an intelligent compiler chooses the best implementation based on the context.^{[You must be registered and logged in to see this link.]}
Managing [You must be registered and logged in to see this link.] acquires a central role in developing parallel applications. The basic steps in designing parallel applications are:
Partitioning The partitioning stage of a design is intended to expose opportunities for parallel execution. Hence, the focus is on defining a large number of small tasks in order to yield what is termed a fine-grained decomposition of a problem.Communication The tasks generated by a partition are intended to execute concurrently but cannot, in general, execute independently. The computation to be performed in one task will typically require data associated with another task. Data must then be transferred between tasks so as to allow computation to proceed. This information flow is specified in the communication phase of a design.Agglomeration In the third stage, development moves from the abstract toward the concrete. Developers revisit decisions made in the partitioning and communication phases with a view to obtaining an algorithm that will execute efficiently on some class of parallel computer. In particular, developers consider whether it is useful to combine, or agglomerate, tasks identified by the partitioning phase, so as to provide a smaller number of tasks, each of greater size. They also determine whether it is worthwhile to replicate data and computation.Mapping In the fourth and final stage of the design of parallel algorithms, the developers specify where each task is to execute. This mapping problem does not arise on uniprocessors or on shared-memory computers that provide automatic task scheduling.
On the other hand, on the [You must be registered and logged in to see this link.], multi-core processors are ideal because they allow many users to connect to a site simultaneously and have independent [You must be registered and logged in to see this link.] of execution. This allows for Web servers and application servers that have much better [You must be registered and logged in to see this link.].

Licensing[[You must be registered and logged in to see this link.]]

Vendors may license some software "per processor". This can give rise to ambiguity, because a "processor" may consist either of a single core or of a combination of cores.

Initially, for some of its enterprise software, [You must be registered and logged in to see this link.] continued to use a per-socket licensing system. However, for some software such as [You must be registered and logged in to see this link.], [You must be registered and logged in to see this link.], and [You must be registered and logged in to see this link.], Microsoft has shifted to per-core licensing.^{[You must be registered and logged in to see this link.]}
[You must be registered and logged in to see this link.] counts an AMD X2 or an Intel dual-core CPU as a single processor^{[[You must be registered and logged in to see this link.]]} but uses other metrics for other types, especially for processors with more than two cores.^{[You must be registered and logged in to see this link.]}

Embedded applications[[You must be registered and logged in to see this link.]]

[You must be registered and logged in to see this link.] operates in an area of processor technology distinct from that of "mainstream" PCs. The same technological drives towards multi-core apply here too. Indeed, in many cases the application is a "natural" fit for multi-core technologies, if the task can easily be partitioned between the different processors.
In addition, embedded software is typically developed for a specific hardware release, making issues of [You must be registered and logged in to see this link.], legacy code or supporting independent developers less critical than is the case for PC or enterprise computing. As a result, it is easier for developers to adopt new technologies and as a result there is a greater variety of multi-core processing architectures and suppliers.
As of 2010, multi-core [You must be registered and logged in to see this link.] devices have become mainstream, with companies such as [You must be registered and logged in to see this link.], [You must be registered and logged in to see this link.], [You must be registered and logged in to see this link.] and [You must be registered and logged in to see this link.] all manufacturing products with eight processors. For the system developer, a key challenge is how to exploit all the cores in these devices to achieve maximum networking performance at the system level, despite the performance limitations inherent in an SMP operating system. To address this issue, companies such as [You must be registered and logged in to see this link.] provide portable packet processing software designed so that the networking data plane runs in a fast path environment outside the OS, while retaining full compatibility with standard OS APIs.^{[You must be registered and logged in to see this link.]}
In [You must be registered and logged in to see this link.] the same trend applies: [You must be registered and logged in to see this link.] has the three-core TMS320C6488 and four-core TMS320C5441, [You must be registered and logged in to see this link.] the four-core MSC8144 and six-core MSC8156 (and both have stated they are working on eight-core successors). Newer entries include the Storm-1 family from [You must be registered and logged in to see this link.] with 40 and 80 general purpose ALUs per chip, all programmable in C as a SIMD engine and [You must be registered and logged in to see this link.] with three-hundred processors on a single die, focused on communication applications.
As of 2016 [You must be registered and logged in to see this link.] multi-core solutions are becoming more common: [You must be registered and logged in to see this link.] Zynq UltraScale+ MPSoC has Quad-core ARM® Cortex™-A53 and Dual-core ARM Cortex-R5. Software solutions such as [You must be registered and logged in to see this link.] are being used to help with inter processor communication.

[You must be registered and logged in to see this link.] Epiphany, a many-core processor architecture which allows up to 4096 processors on-chip, although only a 16 core version has been commercially produced.
[You must be registered and logged in to see this link.] [You must be registered and logged in to see this link.], a multi-core [You must be registered and logged in to see this link.] that also exists in a [You must be registered and logged in to see this link.].
[You must be registered and logged in to see this link.] [You must be registered and logged in to see this link.], a multi-core [You must be registered and logged in to see this link.].
[You must be registered and logged in to see this link.] Am2045, a 336-core Massively Parallel Processor Array (MPPA)
[You must be registered and logged in to see this link.]
- [You must be registered and logged in to see this link.], dual-, triple-, and quad-core of Accelerated Processor Units (APU).
- [You must be registered and logged in to see this link.], [You must be registered and logged in to see this link.] and [You must be registered and logged in to see this link.] family, dual-core desktop processors.
- [You must be registered and logged in to see this link.], dual-, triple-, and quad-core desktop processors.
- [You must be registered and logged in to see this link.], quad-, 6-, and 8-core desktop processors.
- [You must be registered and logged in to see this link.], dual-, quad-, 6-, 8-, 12-, and 16-core server/workstation processors.
- [You must be registered and logged in to see this link.], dual-, triple-, and quad-core processors.
- [You must be registered and logged in to see this link.], dual-, triple-, quad-, and 6-core desktop processors.
- [You must be registered and logged in to see this link.], dual-core entry level processors.
- [You must be registered and logged in to see this link.], dual-core laptop processors.
- [You must be registered and logged in to see this link.] and [You must be registered and logged in to see this link.] multi-core [You must be registered and logged in to see this link.]/[You must be registered and logged in to see this link.] (10 cores, 16 5-issue wide [You must be registered and logged in to see this link.] [You must be registered and logged in to see this link.] per core)
[You must be registered and logged in to see this link.] [You must be registered and logged in to see this link.] BF561, a symmetrical dual-core processor
[You must be registered and logged in to see this link.] [You must be registered and logged in to see this link.] is a fully synthesizable multi-core container for [You must be registered and logged in to see this link.] and [You must be registered and logged in to see this link.] processor cores, intended for high-performance embedded and entertainment applications.
[You must be registered and logged in to see this link.] ModemX, up to 128 cores, wireless applications.
[You must be registered and logged in to see this link.]
- Vega 1, a 24-core processor, released in 2005.
- Vega 2, a 48-core processor, released in 2006.
- Vega 3, a 54-core processor, released in 2008.
Broadcom SiByte SB1250, SB1255, SB1455; BCM 2836 quad-core ARM SoC (designed for the [You must be registered and logged in to see this link.] 2)
[You must be registered and logged in to see this link.]
- CSX700, 192-core processor, released in 2008 (32/64-bit floating point; Integer ALU)
Cradle Technologies CT3400 and CT3600, both multi-core DSPs.
[You must be registered and logged in to see this link.] Octeon, a 32-core [You must be registered and logged in to see this link.] [You must be registered and logged in to see this link.].
[You must be registered and logged in to see this link.] [You must be registered and logged in to see this link.], a 100-core DSP/GPP processor
[You must be registered and logged in to see this link.] QorIQ series processors, up to 8 cores, [You must be registered and logged in to see this link.] [You must be registered and logged in to see this link.].
[You must be registered and logged in to see this link.] [You must be registered and logged in to see this link.] and [You must be registered and logged in to see this link.], dual core [You must be registered and logged in to see this link.] processors.
[You must be registered and logged in to see this link.]
- [You must be registered and logged in to see this link.], a dual-core [You must be registered and logged in to see this link.] processor, released in 2001.
- [You must be registered and logged in to see this link.], a dual-core PowerPC processor, released in 2004.
- [You must be registered and logged in to see this link.], a dual-core PowerPC processor, released in 2007.
- [You must be registered and logged in to see this link.], a 4,6,8-core PowerPC processor, released in 2010.
- [You must be registered and logged in to see this link.], a 12-core PowerPC processor, released in 2013.
- [You must be registered and logged in to see this link.]MP, a dual-core PowerPC processor, used in the Apple [You must be registered and logged in to see this link.].
- [You must be registered and logged in to see this link.], a triple-core, [You must be registered and logged in to see this link.]-capable, PowerPC microprocessor used in the [You must be registered and logged in to see this link.] [You must be registered and logged in to see this link.] game console.
- [You must be registered and logged in to see this link.], a quad-core [You must be registered and logged in to see this link.] processor, released in 2008
- [You must be registered and logged in to see this link.], a quad-core z/Architecture processor, released in 2010
- [You must be registered and logged in to see this link.], a six-core z/Architecture processor, released in 2012
- [You must be registered and logged in to see this link.], an eight-core z/Architecture processor, released in 2015
[You must be registered and logged in to see this link.]
- [You must be registered and logged in to see this link.]
- Danube, a dual-core, MIPS-based, [You must be registered and logged in to see this link.] processor.
[You must be registered and logged in to see this link.]
- [You must be registered and logged in to see this link.], single, dual-core and quad-core processors for netbook, tablets and smartphones systems.
- [You must be registered and logged in to see this link.], the first dual-core processor for the budget/entry-level market.
- [You must be registered and logged in to see this link.], a dual-core processor.
- [You must be registered and logged in to see this link.], a dual-core processor.
- [You must be registered and logged in to see this link.], 2 dual-core dies packaged in a multi-chip module.
- [You must be registered and logged in to see this link.], [You must be registered and logged in to see this link.] and [You must be registered and logged in to see this link.], a family of dual-, quad-, 6-, 8- and 10-core processors, the successor of the [You must be registered and logged in to see this link.] and the [You must be registered and logged in to see this link.].
- [You must be registered and logged in to see this link.], a dual-core processor.
- [You must be registered and logged in to see this link.], 2 single-core dies packaged in a multi-chip module.
- [You must be registered and logged in to see this link.], 2 single-core dies packaged in a multi-chip module.
- [You must be registered and logged in to see this link.], a dual-core processor.
- [You must be registered and logged in to see this link.] (Polaris), a 3.16 GHz, 80-core processor prototype, which the company originally stated would be released by 2011.^{[You must be registered and logged in to see this link.]}
- [You must be registered and logged in to see this link.] dual-, quad-, 6-, 8-, 10-, 12-, 14-, 15-, 16-, 18-, 22-, and 24- core processors.^{[You must be registered and logged in to see this link.]}^{[You must be registered and logged in to see this link.]}^{[You must be registered and logged in to see this link.]}^{[You must be registered and logged in to see this link.]}
- [You must be registered and logged in to see this link.] 57-core, 60-core and 61-core processors.
IntellaSys
- SEAforth 40C18, a 40-core processor^{[You must be registered and logged in to see this link.]}
- SEAforth24, a 24-core processor designed by [You must be registered and logged in to see this link.]
Kalray
- [You must be registered and logged in to see this link.], 256-core processor, released 2012 (256 usable VLIW cores, Network-on-Chip (NoC), 32/64-bit IEEE 754 compliant FPU)
NetLogic Microsystems
- XLP, a 32-core, quad-threaded MIPS64 processor
- XLR, an eight-core, quad-threaded MIPS64 processor
- XLS, an eight-core, quad-threaded MIPS64 processor
[You must be registered and logged in to see this link.]
- [You must be registered and logged in to see this link.] multi-core [You must be registered and logged in to see this link.] (8 cores, 16 [You must be registered and logged in to see this link.] [You must be registered and logged in to see this link.] per core)
- [You must be registered and logged in to see this link.] multi-core [You must be registered and logged in to see this link.] (10 cores, 24 [You must be registered and logged in to see this link.] [You must be registered and logged in to see this link.] per core)
- [You must be registered and logged in to see this link.] multi-core [You must be registered and logged in to see this link.] (10 cores, 24 [You must be registered and logged in to see this link.] [You must be registered and logged in to see this link.] per core)
[You must be registered and logged in to see this link.] [You must be registered and logged in to see this link.], an eight-core microcontroller.
[You must be registered and logged in to see this link.] PC200 series 200–300 cores per device for DSP & wireless
[You must be registered and logged in to see this link.] HAL series tightly coupled 16-256 cores, L1 shared memory, hardware synchronized processor.
Rapport [You must be registered and logged in to see this link.] KC256, a 257-core microcontroller with a PowerPC core and 256 8-bit "processing elements".
[You must be registered and logged in to see this link.] "SiCortex node" has six [You must be registered and logged in to see this link.] cores on a single chip.
[You must be registered and logged in to see this link.]/[You must be registered and logged in to see this link.]/[You must be registered and logged in to see this link.]'s [You must be registered and logged in to see this link.] processor, a nine-core processor with one general purpose [You must be registered and logged in to see this link.] core and eight specialized SPUs (Synergystic Processing Unit) optimized for vector operations used in the [You must be registered and logged in to see this link.] [You must be registered and logged in to see this link.]
[You must be registered and logged in to see this link.]
- [You must be registered and logged in to see this link.] 5200, two-core VLIW processor
- [You must be registered and logged in to see this link.] and UltraSPARC IV+, dual-core processors.
- [You must be registered and logged in to see this link.], an eight-core, 32-thread processor.
- [You must be registered and logged in to see this link.], an eight-core, 64-concurrent-thread processor.
- [You must be registered and logged in to see this link.], a sixteen-core, 128-concurrent-thread processor.
- [You must be registered and logged in to see this link.], an eight-core, 64-concurrent-thread processor.
- [You must be registered and logged in to see this link.], a sixteen-core, 128-concurrent-thread processor.
[You must be registered and logged in to see this link.]
- [You must be registered and logged in to see this link.], a five-core multimedia video processor.
- TMS320TMS320C66, 2,4,8 core dsp.
[You must be registered and logged in to see this link.]
- [You must be registered and logged in to see this link.], a 64-core 32-bit processor
- [You must be registered and logged in to see this link.], a 72-core 64-bit processor
[You must be registered and logged in to see this link.] [You must be registered and logged in to see this link.] quad-core XS1-G4

Free[[You must be registered and logged in to see this link.]]

[You must be registered and logged in to see this link.]

Academic[[You must be registered and logged in to see this link.]]

[You must be registered and logged in to see this link.], 16-core [You must be registered and logged in to see this link.] processor
[You must be registered and logged in to see this link.], [You must be registered and logged in to see this link.] (AsAP)
- 36-core 610 MHz [You must be registered and logged in to see this link.]
- 167-core 1.2 GHz [You must be registered and logged in to see this link.]
[You must be registered and logged in to see this link.], [You must be registered and logged in to see this link.] processor
[You must be registered and logged in to see this link.], [You must be registered and logged in to see this link.] processor
[You must be registered and logged in to see this link.], Sweden, ePUMA processor
[You must be registered and logged in to see this link.], the kilocore, a 1000 core 1.78 GHz processor on a 32 nm IBM process ^{[You must be registered and logged in to see this link.]}

Benchmarks[[You must be registered and logged in to see this link.]]

The research and development of multicore processors often compares many options, and benchmarks are developed to help such evaluations. Existing benchmarks include SPLASH-2, PARSEC, and COSMIC for heterogeneous systems.^{[You must be registered and logged in to see this link.]}

Notes[[You must be registered and logged in to see this link.]]

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[*][You must be registered and logged in to see this link.] [You must be registered and logged in to see this link.] (DSPs) have used multi-core architectures for much longer than high-end general-purpose processors. A typical example of a DSP-specific implementation would be a combination of a [You must be registered and logged in to see this link.] CPU and a DSP [You must be registered and logged in to see this link.]. This allows for the design of products that require a general-purpose processor for user interfaces and a DSP for real-time data processing; this type of design is common in [You must be registered and logged in to see this link.]. In other applications, a growing number of companies have developed multi-core DSPs with very large numbers of processors.

[*][You must be registered and logged in to see this link.] Two types of [You must be registered and logged in to see this link.] are able to use a dual-CPU multiprocessor: partitioned multiprocessing and[You must be registered and logged in to see this link.] (SMP). In a partitioned architecture, each CPU boots into separate segments of physical memory and operate independently; in an SMP OS, processors work in a shared space, executing threads within the OS independently.

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